Iei-integration ICE-DB-9S Manual do Utilizador Página 63
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ICE Module
Page 50
4.3.4 PCI Clock Buffer
The COM Express Specification only supports a single PCI clock signal called
'PCI_CLK' to be used on the carrier board. If there are multiple devices or slots
implemented on the carrier board, a zero delay clock buffer is required to expand the
number of PCI clocks so that each device or each bus slot will be provided with a
separate clock signal.
CLK33M_MINI CARD 5
U2
CY 2309NZSXC-1H
REF
1
CLKA1
2
CLKA2
3
VDD
4
GND
5
CLKB1
6
CLKB2
7
S2
8
S1
9
CLKB3
10
CLKB4
11
GND
12
VDD
13
CLKA3
14
CLKA4
15
CLKOUT
16
CLK33M_SLOT3
CLK33M_BIOS2
C265 10P_4_N_50V1 2
CLK33M_SLOT1 7
CLK33M_SLOT2 7
CLKBUFFER_S2 CLKBUFFER_S1
C17
0.1U_4_Y _16V
C16
10U_8_X_6V3
C18
0.1U_4_Y _16V
C15
10U_8_X_6V3
+V3. 3
FB3
FB30_8_3A
CLK33M_80PORT
C14 10P_4_N_50V1 2
CLK33M_BIOS220
+V3.3_CLKBUF F ER
CLK33M_TPM
C266 10P_4_N_50V1 2
+V3.3_CLKBUFFER
C13 10P_4_N_50V1 2
PCI Clock Buffer
+V3.3_CLK
R6510K_4 1 2
CLKBUFFER_S2
R67@10K_4 1 2
R6210K_4 1 2
CLKBUFFER_S1
+V3.3_CLK
R63@10K_4 1 2
CLK33M_PCI3
C10 10P_4_N_50V1 2
CLK33M_SLOT1
CLK33M_SLOT37
R4533_4 1 2
CLK33M_SIO2
C241 10P_4_N_50V1 2
CLK33M_MINICARD
C11 10P_4_N_50V1 2
C267 10P_4_N_50V1 2
V1.01 Modify
CLK33M_MINIPCI8
R37 33_412
R40 33_412
CLK33M_MINIPCI
C12 10P_4_N_50V1 2
R3833_4 1 2
R4133_4 1 2
R34@33_41 2
CLK33M_SIO2 14
CLK33M_TPM11
R51 33_412
CLK33M_SLOT2
CLK33M_80PORT9
R44 33_412
R47 33_412
+V3.3_CLKBUFFER
R4833_4 1 2
Figure 4-16: PCI Clock Buffer Example
4.3.5 PCI Routing Guideline
Particular attention must be paid to the PCI clock routing. The PCI Local Bus
specification requires a maximum propagation delay for the clock signals of 10ns
within a propagation skew of 2ns @ 33MHz between the several clock signals. The
COM Express Specification allows 1.6ns ± 0.1ns @ 33MHz propagation delay for the
PCI clock signal beginning from the module pin to the destination pin of the PCI device.
The propagation delay is dependent on the trace geometries, PCB stack-up and the
PCB dielectric constant. Calculating using a typical propagation delay value of
180ps/inch for an internal layer clock trace of the carrier board, a maximum trace
length of 8.88 inches is allowed.
The clock trace from the COM Express module to a PCI bus slot should be 2.5 inches
shorter because PCI cards are specified to have 2.5 inches of clock trace length on
the card itself. PCI clock signals should be routed as a single ended trace with a trace
impedance of 55Ω. To reduce EMI, a single ground referenced internal layer is
recommended. The clock traces should be separated as far as possible from other
- ICE Module 1
- Revision 2
- Copyright 3
- Table of Contents 4
- List of Figures 9
- List of Tables 12
- 1 Introduction 14
- 1.1 Introduction 15
- 1.3 Reference Documents 17
- 2 ICE Module Overview 18
- 2.1 Chapter Overview 19
- 2.2 ICE Specifications 20
- 2.2.1 ICE-9152-R10 21
- Page 16 29
- 2.2.5 ICE-GM45A-R10 29
- 2.2.6 ICE-DB-9S-R10 30
- 2.3 Performance 32
- 3 Pin Assignments 33
- 3.1 Chapter Overview 34
- 3.3 Signal Table Terminology 36
- Page 24 37
- 4 Signal Description and 42
- Routing Guideline 42
- Page 30 43
- 4.1.1 Signal Description 43
- 4.1.3 SDVO 46
- AC Coupling Cap 50
- 4.2 PCI Express 51
- 4.2.1 Signal Description 52
- VCC1.5/1A 54
- Page 42 55
- 4.3 PCI 60
- 4.4.1 Signal Description 64
- Page 54 67
- 4.5.1 Signal Description 67
- from Semtech 72
- 4.6 LVDS 74
- 3.3V(Default) 75
- J_VLVDS1 75
- 4.8 Reference Circuit 78
- 4.9 IDE 79
- IDE Connector 80
- CF Connector 81
- 4.10 TV-Out 82
- +V5_KB_R +V5_KB_RR 90
- 4.13 VGA 92
- 4.14 Miscellaneous 95
- CPU FAN W/FAN Control 97
- SYSTEM FAN W/FAN Control 97
- CLEAR CMOS/Super CAP 98
- 5 PCB Stack and 99
- Power Deliver Design 99
- 5.1 Chapter Overview 100
- 5.2 Microstrip or Stripline 100
- 5.3 PCB Stackup Example 100
- Page 90 103
- T0 T1 T2 T3 T4 T5 T6 T7 T8 105
- AT Power 106
- T0 T1 T2 T3 T4 T5 T6 107
- Chapter 108
- 6.1 Chapter Overview 109
- 6.3 Connector Footprint 111
- 6.4 COM Express Form Factors 112
- 6.5 Heat Spread 113
- Page 101 114
- 6.6 Design Notes 116
- Page 104 117
- A ICE Module Design 120
- Schematic Check List 120
- Page 108 121
- Page 109 122
- Page 110 123
- Page 111 124
- Page 112 125
- B Application Notes 129
- B.1 Terminology 130
- B.2 Updating BIOS Version 130
- Page 119 132
- Page 120 133
- Page 121 134
- 6.7.2 Using DOS Command 134
- Page 122 135
- A.1 RTC Overview 136
- B Reference Carrier 137
- Board Schematic 137
- PCI ROUTING 138
- Cover Page 138
- ATX/AT Power 139
- COMExpress 139
- F119 ICE-DB-9S-R10 140
- IEI ELECTRONICS INC 140
- PCI Clock Buffer 141
- PCIE Clock Buffer 141
- Mini PCI Express 142
- Express Card 142
- PCIEX1_Slot1 142
- PCIEX1_Slot2 142
- D23, REQ#0,GNT#0,INT#AB 145
- 7-Segment LED with Common GND 146
- PCIEX1_Slot3 147
- PCIEX1_Slot4 147
- W83627EHG 150
- FLOPPY(only Device A) 152
- Front_Audio 155
- CD_IN(Reserve) 155
- Audio Rear Jack 156
- Audio Rear Header 156
- SPDIF Connector(Reserve) 156
- COM Module 159
- Express Card Module 159
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