Iei-integration PCISA-945GSE v1.01 Manual do Utilizador Página 41
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PCISA-945GSE CPU Card
Page 23
Integrated 10/100/1000 transceiver
Auto-Negotiation with Next Page capability
Supports PCI Express™ 1.1
Supports pair swap/polarity/skew correction
Crossover Detection & & Auto-Correction
Wake-on-LAN and remote wake-up support
Microsoft® NDIS5, NDIS6 Checksum Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send and Giant send) support
Supports Full Duplex flow control (IEEE 802.3x)
Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
Supports IEEE 802.1P Layer 2 Priority Encoding
Supports IEEE 802.1Q VLAN tagging
Serial EEPROM
Transmit/Receive on-chip buffer support
Supports power down/link down power saving
Supports PCI MSI (Message Signaled Interrupt) and MSI-X
Supports Receive-Side Scaling (RSS)
2.5.9 SPI Bus Components
The Intel® ICH7M SPI bus is connected to components listed below:
BIOS chip
2.5.9.1 SPI BIOS
The 4-pin Serial Peripheral Interface (SPI) is connected to an SPI BIOS chip. A licensed
copy of AMI BIOS is preinstalled on the SPI BIOS chip. A master-slave protocol is used for
communication on the SPI bus. The slave is connected to the Intel® ICH7M and is
implemented as a tri-state bus. The SPI BIOS is located on the reverse side of the JSPI1
jumper.
- PCISA-945GSE 1
- Revision 2
- Copyright 3
- Manual Conventions 4
- Packing List 6
- Table of Contents 7
- List of Figures 13
- List of Tables 16
- BIOS Menus 18
- 1 Introduction 19
- 1.1 Introduction 20
- 1.2 Overview Photo 21
- 1.4 Technical Specifications 23
- 2 Detailed Specifications 26
- 2.1 Dimensions 27
- Page 10 28
- 2.2 Data Flow 29
- 2.3 Intel® Atom™ Processor 30
- Page 15 33
- 2.4.2.4 SDVO and DVI 33
- Page 16 34
- Page 25 43
- 2.6.3 Power Consumption 43
- 3 Unpacking 44
- 3.1 Anti-static Precautions 45
- 3.2 Unpacking 45
- 3.3 Unpacking Checklist 46
- Page 29 47
- 3.3.2 Optional Items 47
- Page 30 48
- 4 Connectors 49
- Page 32 50
- 4.1.1 Layout 50
- Page 33 51
- Page 34 52
- PIN NO. DESCRIPTION 53
- 2 PS-ON 53
- 1 Battery+ 56
- 2 Battery 56
- Page 40 58
- 7Figure 4-10 60
- 7Table 4-10 60
- Page 44 62
- 4.2.10 Front Panel Connector 62
- 3 PWR_BTN- 4 PWR_LED 63
- 7 HDD_LED- 8 RESET 63
- Page 46 64
- 7Figure 4-14 65
- 7Table 4-14 65
- Page 49 67
- 7Figure 4-17 68
- 7Table 4-17 68
- 7Figure 4-19 70
- 7Table 4-19 70
- Page 55 73
- 4.2.20 TV Out Connector 73
- 8Figure 4-23 74
- 8Table 4-23 74
- 1 MDIA3- 5 MDIA1+ 76
- 2 MDIA3+ 6 MDIA2+ 76
- 3 MDIA2- 7 MDIA0 76
- 4 MDIA1- 8 MDIA0+ 76
- 8Table 4-25 77
- 8Figure 4-24 77
- 8Table 4-26 77
- 8Figure 4-26 and 8Table 4-27 77
- 5 Installation 79
- 5.1 Anti-static Precautions 80
- Page 64 82
- 5.2.2 Installation Checklist 82
- 5.4 CF Card Installation 83
- Page 66 84
- Page 67 85
- NOTE: 86
- Page 69 87
- 5.6.1 AT/ATX Power Selection 87
- Page 70 88
- 5.6.2 Clear CMOS Jumper 88
- 5.7 Chassis Installation 91
- Page 75 93
- Page 77 95
- Page 78 96
- Page 79 97
- Page 80 98
- Page 81 99
- 5.8.7 SATA Drive Connection 99
- PCISA-945GSE CPU Card 100
- Page 82 100
- Page 84 102
- Page 85 103
- 5.9.1 LAN Connection 103
- Page 86 104
- Page 87 105
- 5.9.3 VGA Monitor Connection 105
- Page 88 106
- 6 BIOS Setup 107
- 6.1 Introduction 108
- Page 92 110
- 6.3 Advanced 111
- Page 94 112
- Page 95 113
- 6.3.1 CPU Configuration 113
- Configuration 114
- 86.3.2.1 appear 115
- Page 103 121
- 6.3.3 Floppy Configuration 121
- DEFAULT 122
- Page 109 127
- Page 110 128
- 6.4 PCI/PnP 139
- 6.5 Boot 142
- 6.6 Security 149
- 6.7 Chipset 150
- Page 136 154
- Page 137 155
- 6.8 Exit 157
- Page 140 158
- 7 Software Installation 159
- Page 142 160
- Page 143 161
- Page 144 162
- Page 145 163
- Page 146 164
- Page 147 165
- 7.4 VGA Driver Installation 166
- Page 149 167
- Page 150 168
- EXT to continue 169
- 7.5 LAN Driver Installation 170
- Page 153 171
- Page 154 172
- Page 155 173
- Page 156 174
- Page 157 175
- Page 158 176
- Page 159 177
- 7.7 iSMM Installation 178
- Page 161 179
- Page 162 180
- Page 163 181
- Page 164 182
- Page 165 183
- Page 166 184
- A BIOS Options 185
- B Terminology 189
- Page 172 190
- Page 173 191
- Page 174 192
- C Digital I/O Interface 193
- C.1 Introduction 194
- C.2 DIO Connector Pinouts 194
- D Watchdog Timer 196
- Page 179 197
- E Address Mapping 199
- E.2 Input/Output (IO) 200
- Page 183 201
- E.3 Interrupt Request (IRQ) 202
- E.4 Memory 203
- F Hazardous Materials 204
- Disclosure 204
- Mercury 205
- Page 188 206
- Page 189 207
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