Iei-integration NANO-9453 v1.0 Manual do Utilizador descarregar pdf (Página 170)

NANO-9453 EPIC Motherboard

Page 152

 3 nanoseconds

 DRAM RAS# to CAS# Delay [6 DRAM Clocks]

Use the DRAM RAS# to CAS# Delay option to specify the number of clock cycles must

elapse between sending a RAS (row address strobe) signal and the CAS (column address

strobe) signal. A pause is required between the RAS signal and the CAS signal to ensure

the memory is correctly addressed. (To be able to change this configuration option the

Configure DRAM Timing by SPD configuration option must be set to “Disabled”)

Configuration options are listed below:

 2 DRAM Clocks

 3 DRAM Clocks

 4 DRAM Clocks

 5 DRAM Clocks

 6 DRAM Clocks DEFAULT

 DRAM RAS# Precharge [6 DRAM Clocks]

Use the DRAM RAS# Precharge option to set the speed at which the RAM terminates the

access of one row and start accessing another. (To be able to change this configuration

option the DRAM RAS# Precharge configuration option must be set to “Manual”) The

following configuration options are available

 2 DRAM Clocks

 3 DRAM Clocks

 4 DRAM Clocks

 5 DRAM Clocks

 6 DRAM Clocks DEFAULT

 DRAM RAS# Activate to Precha [15 DRAM Clocks]

Use the DRAM RAS# Activate to Precha option to specify the length of the delay

between the activation and precharge commands for the RAS signal. That is how long

after activation can the access cycle be started again. This influences row activation time

that is considered when memory has hit the last column in a specific row, or when an

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Iei-integration NANO-9453 v1.0 Manual do Utilizador Página 170