Iei-integration NANO-9453 v1.0 Manual do Utilizador Página 82
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NANO-9453 EPIC Motherboard
Page 64
5.1 Anti-static Precautions
WARNING:
Failure to take ESD precautions during the installation of the
NANO-9453 may result in permanent damage to the NANO-9453 and
severe injury to the user.
Electrostatic discharge (ESD) can cause serious damage to electronic components,
including the NANO-9453. Dry climates are especially susceptible to ESD. It is therefore
critical that whenever the NANO-9453, or any other electrical component is handled, the
following anti-static precautions are strictly adhered to.
Wear an anti-static wristband: - Wearing a simple anti-static wristband can
help to prevent ESD from damaging the board.
Self-grounding:- Before handling the board touch any grounded conducting
material. During the time the board is handled, frequently touch any
conducting materials that are connected to the ground.
Use an anti-static pad: When configuring the NANO-9453, place it on an
antic-static pad. This reduces the possibility of ESD damaging the
NANO-9453.
Only handle the edges of the PCB:-: When handling the PCB, hold the PCB
by the edges.
- NANO-9453 EPIC Motherboard 1
- Revision 2
- Copyright 3
- Packing List 4
- Table of Contents 5
- List of Figures 11
- List of Tables 14
- BIOS Menus 16
- Glossary 17
- Page xix 18
- 1 Introduction 19
- 1.1 Introduction 20
- 1.2 NANO-9453 Overview 21
- 2 Detailed Specifications 25
- 2.1 Overview 26
- 2.2 Dimensions 26
- 2.3 Data Flow 28
- 2.4 Compatible Processors 29
- 2.5 Intel 30
- 945GM Northbridge Chipset 30
- 2.6 Intel 33
- ICH7M Southbridge Chipset 33
- 2.7 PCIe Bus Components 36
- 2.8 LPC Bus Components 37
- Page 22 40
- Page 24 42
- 3 Unpacking 43
- 3.1 Anti-static Precautions 44
- 3.2 Unpacking 44
- 3.3 Unpacking Checklist 45
- Page 28 46
- Page 30 48
- 4 Connector Pinouts 49
- Page 34 52
- PIN NO. DESCRIPTION 55
- 2 PS_ON# 55
- 3 +5V Standby 55
- Page 38 56
- 4.2.5 Compact Flash Socket 57
- Page 40 58
- Page 42 60
- 4.2.7 Fan Connector 60
- Page 44 62
- 4.2.9 IDE Connector(44-pin) 62
- 4.2.11 LVDS LCD Connector 65
- 4.2.14 PCI-104 Slot 69
- 30 -12V TBD2 TBD GND/3.3V 72
- Page 56 74
- 1 VCC 2 GND 76
- 3 DATA- 4 DATA+ 76
- 5 DATA+ 6 DATA 76
- 7 GND 8 VCC 76
- PIN DESCRIPTION PIN 78
- DESCRIPTION 78
- 1 VCC 5 VCC 79
- 2 DATA- 6 DATA 79
- 3 DATA+ 7 DATA+ 79
- 4 GROUND 8 GROUND 79
- Figure 4-24: VGA Connector 80
- 5 Installation 81
- 5.1 Anti-static Precautions 82
- Read the user manual: 83
- Page 66 84
- 5.2.2 Installation Checklist 84
- NOTE: 93
- CF Card Setup Description 94
- Open Slave Default 94
- Short Master 94
- 5.4.2 Clear CMOS Jumper 95
- Short 1-2 RS-232 Default 96
- Short 3-4 RS-422 96
- Short 5-6 RS-485 96
- Short 2-3 +5V LVDS 97
- Short 1-2 VCC 98
- Short 2-3 VCC3 98
- 5.5 Chassis Installation 100
- USB cable 101
- RS-232/422/485 cable 101
- LPT cable 101
- ATX power cable 101
- Page 86 104
- Page 92 110
- Figure 5-25: USB Connector 115
- Page 98 116
- 6 AMI BIOS 117
- 6.1 Introduction 118
- 6.2 Main 120
- 6.3 Advanced 121
- Page 105 123
- Primary IDE Master 125
- Primary IDE Slave 125
- Secondary IDE Master 125
- Secondary IDE Slave 125
- Page 108 126
- DEFAULT 132
- CPU Temp. Limit of OFF 136
- Page 120 138
- WARNING: 138
- Page 121 139
- Page 133 151
- 6.3.9 USB Configuration 151
- 6.4 PCI/PnP 155
- 6.5 Boot 161
- CD/DVD 164
- Page 147 165
- 6.6 Security 166
- 6.7 Chipset 167
- Page 152 170
- IGD DEFAULT 172
- PCI/IGD 172
- Page 156 174
- Page 157 175
- Page 158 176
- 6.8 Exit 177
- Page 160 178
- 7 Driver Installation 179
- 7.2 Driver CD Auto-run 180
- ES to continue the setup 182
- Page 167 185
- Page 168 186
- Page 169 187
- Page 170 188
- Page 171 189
- Page 172 190
- NEXT to 191
- EL during POST 191
- EXT. See Figure 7-24 193
- INISH” button. Step 0: 194
- EXT” button. The install 196
- ” button 197
- Page 181 199
- Page 182 200
- Page 183 201
- Page 184 202
- Page 185 203
- Page 186 204
- A BIOS Options 205
- Page 192 210
- B DIO Interface 211
- B.2 DIO Connector Pinouts 212
- Page 196 214
- C Watchdog Timer 215
- Page 200 218
- D Address Mapping 219
- D.1 Address Map 220
- D.3 IRQ Mapping Table 221
- D.4 DMA Channel Assignments 221
- Page 204 222
- E Intel 223
- Matrix Storage 223
- Manager 223
- E.1 Introduction 224
- E.2 Features and Benefits 225
- E.3 Accessing the Intel 225
- Matrix Storage Manager 225
- E.4 RAID Configuration 226
- NTER. See Figure E-1 227
- NTER to 227
- NTER. See Figure E-8 231
- NTER. See Figure E-9 232
- NTER. See Figure E-12 234
- NTER. See Figure E-13 234
- F Index 237
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